1. Field
Exemplary embodiments of the present invention relate to a non-volatile memory device and a method of fabricating the same, and more particularly, to a non-volatile memory device that includes a plurality of memory cells stacked vertically from a substrate, and a method of fabricating the same.
2. Description of the Related Art
A non-volatile memory device is a memory device in which stored data is maintained as it is even when power supply is cut off. Currently, a variety of non-volatile memory devices, for example, a NAND flash memory and the like are widely utilized.
Recently, as an improvement in the degree of integration of a two-dimensional non-volatile memory device which forms a single memory cell over a silicon substrate reaches the limit, a variety of three-dimensional non-volatile memory devices are proposed in which a plurality of memory cells is stacked vertically from the silicon substrate.
A general three-dimensional non-volatile memory device includes a channel extending in a vertical direction from a substrate, a source selection transistor, a plurality of memory cells, and a drain selection transistor which are sequentially stacked along the channel, a source line which is formed by ion injection into the substrate and connected to one end of the source selection transistor, and a bit line which is disposed over the drain selection transistor and connected to one end of the drain selection transistor. In such a structure, since the source line is formed by the ion injection process, there is a problem in which the resistance of the source line is very increased.
Meanwhile, in the “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices”, VLSI Technology, 2009 symposium, ISBN 978-4-86348-009-4, pp. 136-137 which is a document disclosed on Jun. 16 to 18, 2009, there is disclosed a flash memory called a “PBiCS” structure. Unlike the general three-dimensional non-volatile memory device in which the bit and source lines are respectively disposed over and under the stacked memory cell, the flash memory has a structure in which all of bit and source lines are disposed over a stacked memory cell. Accordingly, a metal source line may be formed, thereby enabling the resistance of the source line to be reduced.
However, in the PBiCS structure, a channel is separated from a substrate body. Thus, it may impossible to perform an erase operation in an F-N tunneling manner that applies a high voltage to the substrate body to inject a charge storage layer of the memory cell with holes, as the related art. Instead of that, data is erased in a manner of injecting a channel with holes created by applying a high voltage to a selection gate to generate a GIDL (Gate Induced Drain Leakage) current. Incidentally, source and drain junctions on the upper end of the channel should sufficiently overlap with the selection gate in order to generate the GIDL current. For this reason, there are caused problems such as an increase in leakage current of the selection gate, a deterioration of switching characteristics, a dispersion increase of a threshold voltage, and an inability to adjust the threshold voltage. As a result, there are problems that it is difficult to control the erase operation and efficiency is deteriorated.
In addition, in the PBICS structure, the channel has a U-shape while being entirely formed of polysilicon. Therefore, there are problems in that an operating current is decreased equal to or more than 50% and a selection transistor has poor characteristics, compared with a structure having an I-shaped channel.
Accordingly, there is a need to realize a three-dimensional non-volatile memory device having a new structure that can solve the above-mentioned problems.